Article ID: 000082802 Content Type: Troubleshooting Last Reviewed: 01/20/2014

Why do I see different timing in the Quartus II timing report and the TimeQuest timing analyzer?


  • Quartus® II Subscription Edition
    Description Due to a problem in the Quartus® II software version 13.1, you may see the timing reported in the Quartus II software timing report is different from the timing reported in the TimeQuest Timing Analyzer for Stratix® V devices. The timing reported by the Quartus II software timing report is correct.
    Resolution To work around this problem, follow these steps in the TimeQuest Timing Analyzer:
      1. Netlist > Delete Timing Netlist
      2. Netlist > Create Timing Netlist
      3. In the prompted property menu, append "-force_dat" to the Tcl command and click OK.
      4. Read the Synopsys Design Constraints (.SDC) file and update timing netlist.

    Following these steps, report timing produces the same timing report as the Quartus II software.

    This problem is scheduled to be fixed in a future release of the Quartus II software.

    Related Products

    This article applies to 1 products

    Stratix® V GX FPGA