Article ID: 000082795 Content Type: Troubleshooting Last Reviewed: 09/12/2012

Why do I see PCIe core clock frequency at 12.5MHz under the Clock Settings tab of Qsys GUI?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description If you set the number of lanes to 2 for the IP Compiler for PCI Express, the PCIe core clock frequency would be display as 12.5MHz at the Clock Settings tab of Qsys GUI. This issue will be fixed in Quartus II v11.1SP1.
    Resolution

    Meanwhile you can modify line#1503 of pcie_parameters_validation.tcl in (<Quartus II installation directory>\ip\altera\altera_pcie\altera_pcie_avmm)

    from:

                            set_parameter_value core_clk_freq 125

    to:

    set_parameter_value core_clk_freq 1250

     

    to get around this issue.

    Related Products

    This article applies to 1 products

    Cyclone® IV GX FPGA

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