Article ID: 000082751 Content Type: Troubleshooting Last Reviewed: 10/30/2012

Why is the PCI express address incorrect when using the Tx Slave Avalon-MM port on the IP Compiler for PCI Express in QSys?

Environment

  • Quartus® II Subscription Edition
  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a bug in the IP Compiler for PCI Express® in versions 11.1, 11.1sp1 and 11.1sp2 of the Quartus® II software, addresses may not be translated correctly when using the TX Avalon®-MM slave port to generate PCI Express requests when all bits of ByteEnable are not asserted.

    For example, if PCI Express requests are generated with only the upper dword enabled on the TX Avalon-MM slave port, the PCI express request that is generated will be a single dword request but with the address of the lower dword.

    This problem will be fixed in a future version of the Quartus II software.

    Resolution

    A patch is available to fix this problem for the Quartus II software version 11.1sp1.  Download and install patch 1.16 from the appropriate link below.

    Related Products

    This article applies to 1 products

    Stratix® IV GX FPGA

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