Article ID: 000082745 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does the 'rx_dataout' of Stratix® II GX transceiver channel stuck at a fixed value under some conditions


  • Stratix® II GX FPGA

In Stratix® II GX device, when an invalid input signal is received, random data is expected on the deserialized output data of the Clock and Data Recovery (CDR) block. However, in some cases, even with an invalid input signal, the CDR deserialized output may have a fixed clock-like data pattern(0101.. or 1010..). In this scenario, when 8b/10b is enabled, the receive output (rx_dataout) on the PLD interface will have a fixed Hex A4 or Hex B5 (decoded value of 0101..or 1010..). The status signals namely, rx_disperr, rx_errdetect,  and the rx_syncstatus signal does not change to indicate that the fixed data is invalid.

This issue is independent of the ALT2GXB configuration,  transceiver settings, or device families in Stratix II GX. However, once the issue is observed on a particular transceiver channel for an invalid input, it can be reproduced on the same channel under all conditions. The receiver input can have invalid signal due to unplugging the serial input cable or tri-stating the upstream source driver.

Based on the CDR mode (Manual or Automatic), use the following workarounds for this issue

CDR set in Automatic mode:  In Automatic mode, when the CDR receives and invalid input signal, it transitions repeatedly between Lock to Reference (LTR) and Lock to Data (LTD).  The 'rx_freqlocked' signal that is available to the PLD logic toggles between high and low to indicate this condition. Therefore, in automatic mode, use the 'rx_freqlocked' as one of the parameters in the PLD logic to determine whether the received input data is valid.

CDR set in Manual mode: In Manual mode,  since the user controls the CDR transition from LTR to LTD, the 'rx_freqlocked' stays high when the CDR is set to LTD. Therefore in this mode, you cannot use the 'rx_freqlocked' signal to determine whether the input signal in invalid. You have to design an external PPM detector that compares the reference clock frequency with the recovered clock frequency. Since the recovered clock frequency starts drifting upon receiving invalid input signal, the output of the designed PPM detector in the user logic should be used to determine whether the receved input signal is invalid.

In addition to the above workarounds, if you have configured the Stratix II GX transceiver channel for PIPE protocol, you can also the 'pipeelecidle' status signal to detect an invalid serial input. The 'pipeelecidle'  is available only in PIPE mode. 




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