Article ID: 000082710 Content Type: Product Information & Documentation Last Reviewed: 07/23/2013

How do I resolve timing failures on the Stratix V GX Reconfiguration Controller IP pmatestbussel bus when I recompile my design in Quartus II software version 13.0?

Environment

  • Stratix® V GT FPGA
  • Stratix® V GX FPGA
  • Arria® V GZ FPGA
  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    To resolve timing failures reported on the pmatestbussel bus when compiling your design in Quartus II software version 13.0, you should follow these steps:

    1. Regenerate the Transceiver Reconfiguration Controller IP in Quartus 13.0.
    2. Verify the top level 'derive_pll_clocks' SDC command is executed before sourcing the alt_xcvr_reconfig.sdc file.
    3. If the Transceiver TX PLL is instantiated as an external Tx PLL, replace the following constraint in the alt_xcvr_reconfig.sdc file.

    Replace

    • set_clock_groups -asynchronous -group [get_clocks {*xcvr_native*avmm*pmatestbussel[0]}]

    With

    • set_clock_groups -asynchronous -group [get_clocks {*hssi_avmm_interface_inst|pmatestbussel[0]}]

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