The rx_cda_reset input port of the ALTLVDS_RX malfunction is not supported in Arria® V GX, GT, SX, and ST devices and Cyclone® V devices beginning in the Quartus® II software version 12.1. The bitslip, also referred to as the data alignment, is set to the zero latency position (reset) by asserting pll_areset.
Note the RTL simulation model does not reset the bitslip when pll_areset is asserted. This is an issue only with the RTL simulation model. The RTL simulation model is scheduled to be fixed in a future version of the Quartus II software.
The bitslip latency will be set to the zero position when pll_areset is asserted in gate level simulation, and in hardware.