Article ID: 000082655 Content Type: Product Information & Documentation Last Reviewed: 03/16/2023

How can I reset the bitslip in the ALTLVDS_RX mega function in Arria® V and Cyclone® V devices?

Environment

    Quartus® II Subscription Edition
    Avalon ALTPLL
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The rx_cda_reset input port of the ALTLVDS_RX malfunction is not supported in Arria® V GX, GT, SX, and ST devices and Cyclone® V devices beginning in the Quartus® II software version 12.1.  The bitslip, also referred to as the data alignment, is set to the zero latency position (reset) by asserting pll_areset.

Note the RTL simulation model does not reset the bitslip when pll_areset is asserted.  This is an issue only with the RTL simulation model.  The RTL simulation model is scheduled to be fixed in a future version of the Quartus II software.

 

 

Resolution

The bitslip latency will be set to the zero position when pll_areset is asserted in gate level simulation, and in hardware.

Related Products

This article applies to 10 products

Cyclone® V GX FPGA
Arria® V GX FPGA
Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Arria® V SX SoC FPGA
Arria® V GT FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Cyclone® V E FPGA
Cyclone® V SE SoC FPGA

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