Article ID: 000082611 Content Type: Product Information & Documentation Last Reviewed: 08/13/2012

How long does the transceiver on-chip termination calibration process take for Stratix IV GX/T and Arria II GX/Z devices?

Environment

  • Arria® II GZ FPGA
  • Arria® II GX FPGA
  • Stratix® IV GT FPGA
  • Stratix® IV GX FPGA
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Description

The transceiver on-chip termination calibration process takes 33,000 cal_blk_clk cycles from the de-assertion of the cal_blk_powerdown signal on Stratix® IV GX/T and Arria® II GX/Z devices.

This time period applies to calibration blocks that control either one, or multiple transceiver blocks.

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