Article ID: 000082534 Content Type: Product Information & Documentation Last Reviewed: 04/03/2023

How do I determine a loss of alignment when using the Intel® Stratix® 10 E-Tile Hard IP for Ethernet Intel® FPGA IP in 100G mode with PCS (528,514)RSFEC or PCS (544,514)RSFEC IP?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Ethernet
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Currently there is no exposed port on the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel® FPGA IP when in 100G mode with either PCS (528,514)RSFEC or PCS (544,514)RSFEC IP that indicates a loss of alignment.

    Resolution

    This has been fixed in the Intel® Quartus® Prime Software v18.1.1.

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 TX FPGA

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