Article ID: 000082480 Content Type: Product Information & Documentation Last Reviewed: 08/27/2013

How do I make a location assignment for fractional PLLs in Stratix V devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You can make a location assignment for fractional PLLs in Stratix® V devices in the Quartus® II software by using the Assignment Editor and these steps:

  1. In the Assignment Editor, set the Category to "Locations".
  2. In the "To" column, select the PLL instance using the node finder.  It is helpful to narrow down the search by selecting *.gpll* as the filter.
  3. In the "Assignment Name" column, select "Location".
  4. Double click in the "Value" column and select "Fractional PLL" as the "Element" from the drop list.  This will allow you to specify valid X, Y, and N locations from a drop list.
  5. Add "~FRACTIONAL_PLL" to the PLL instance assignment in order to assign the PLL location correctly.

For example, the node name in the "To" column should look similar to the following:

 altpll0:inst|altpll0_0002:altpll0_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL

An example .qsf setting would be:

set_location_assignment FRACTIONALPLL_X0_Y122_N0 -to " altpll0:inst|altpll0_0002:altpll0_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL"

Resolution

 

Related Products

This article applies to 1 products

Stratix® V GX FPGA

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