Article ID: 000082380 Content Type: Troubleshooting Last Reviewed: 06/29/2018

When using the Intel® Arria® 10 PCI* Express Hard IP, why are message data allocated vectors(0x05c) not writeable in the MSI capability structure when multiple message enable is set?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
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    Critical Issue

    Description

    In Intel® Arria® 10 FPGAs, the PCIe* message data allocated vector bits are not writeable when multiple message enable is set.

    For example, when multiple message enable is set to 3'b010, and  32'hFFFFFFFF is written into configuration space Message Data Field, and user interrupt inputs are all 0, then software can only read 32'hFFFFFFFC.

    This is a minor bug since the MSI packet generated by Intel® Arria® 10 Had IP is still correct.

    Resolution

    There is no plan to fix this problem. Your design must be aware that message data allocated vector bits are not always readable by SW when multiple message enable are set.

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