When using the Intel® Arria® 10 PCI* Express Hard IP, why are message data allocated vectors(0x05c) not writeable in the MSI capability structure when Multiple Message Enable is set?

In Intel® Arria® 10 FPGAs, the PCIe* message data allocated vector bits are not writeable when Multiple Message Enable is set.

For example, when Multiple Message Enable is set to 3'b010, and  32'hFFFFFFFF is written into the configuration space Message Data Field, and user interrupt inputs are all 0, then the software can only read 32'hFFFFFFFC.

This is a minor bug since the MSI packet generated by Intel® Arria® 10 Hard IP is still correct.

There is no plan to fix this problem. Your design must be aware that message data allocated vector bits are not always readable by SW when Multiple Message Enable are set.