Article ID: 000082371 Content Type: Troubleshooting Last Reviewed: 06/22/2018

Why does the Intel® Arria® 10 fPLL IP generate the wrong phase shift?

Environment

  • Intel® Quartus® Prime Pro Edition
  • fPLL Intel® Arria® 10 Cyclone® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with the Intel® Quartus® Prime software version 17.1, you may see the fPLL IP for Intel®  Arria® 10 sets an incorrect phase shift. It generates double the desired phase shift.

    Resolution

    To work around this problem, set a phase shift to be half of what you require.

    To check phase shift settings, use the TimeQuest Timing Analyzer command "derive_pll_clocks", it reports the actual hardware configuration.

    This problem will be fixed in a future release of the Intel® Quartus® Prime software.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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