Description
Due to a problem with the Intel® Quartus® Prime software version 17.1, you may see the fPLL IP for Intel® Arria® 10 sets an incorrect phase shift. It generates double the desired phase shift.
Resolution
To work around this problem, set a phase shift to be half of what you require.
To check phase shift settings, use the TimeQuest Timing Analyzer command "derive_pll_clocks", it reports the actual hardware configuration.
This problem will be fixed in a future release of the Intel® Quartus® Prime software.
