Article ID: 000082329 Content Type: Troubleshooting Last Reviewed: 12/03/2012

Quartus II Fitter Generates 0 ppm Critical Warnings When Regenerating Underlying PHY IP Cores in 40GbE and 100GbE MAC and PHY IP Cores

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The 40GbE and 100GbE MAC and PHY IP cores include PHY IP cores generated by the MegaWizard Plug-In Manager. When regenerating PHY IP cores with a later Quartus II software revision, the Quartus Fitter may generate Critical Warnings regarding 0 ppm relationships between various PMA channels.

    Resolution

    This issue is fixed in the 12.1 Quartus software release of the IP core.

    For the 12.0 release of the IP core, the Quartus Fitter checks the required 0-ppm variation between clocks that transmit or receive serial data on different PMA lanes. The tool does not recognize the clocking architecture placed above the PHY lanes; when no additional information is provided the following 0 ppm Critical Warning is produced by the Fitter in the Quartus II software version 12.0 for the Stratix IV and Stratix V devices:

    Critical Warning (178012): Coreclk source from 10G RX PCS atom alt_e100_pma:pma|alt_e100_e10x10:gx|.....si_10g_rx_pcs|wys do not have same 0ppm source with respected to PCS internal clock because rx_pld_clk source of 10G RX PCS atom alt_e100_pma:pma|alt_e100_e10x10:....�

    To fix this problem, the .qsf file of the top-level design must contain specific constraints.

    Designs based on the Stratix IV device must contain the following constraints:

    • set_instance_assignment -name GXB_0PPM_CORE_CLOCK ON -from <TOP_LEVEL_PINS_CONNECTED_TO_TXPMA>* -to <TOP_LEVEL_PINS_CONNECTED_TO_TXPMA>*
    • set_instance_assignment -name GXB_0PPM_CORE_CLOCK ON -from <TOP_LEVEL_PINS_CONNECTED_TO_RXPMA>* -to <TOP_LEVEL_PINS_CONNECTED_TO_RXPMA>*

    Designs based on the Stratix V device must contain the following constraints:

    • set_instance_assignment -name GXB_0PPM_CORECLK ON -to <TOP_LEVEL_PINS_CONNECTED_TO_TXPMA>*
    • set_instance_assignment -name GXB_0PPM_CORECLK ON -to <TOP_LEVEL_PINS_CONNECTED_TO_RXPMA>*

    Examples of these settings can be found in the .qsf files for the various wrappers under the alt_eth_40g/quartus_synth/wrappers/ and alt_eth_100g/quartus_synth/wrappers/ directories. For example, the alt_100g_phy wrapper in the alt_eth_100g/quartus_synth/wrappers/ directory contains alt_e100_phy_siv.qsf and alt_e100_phy_siv.qsf files with the appropriate constraints described above.

    Related Products

    This article applies to 2 products

    Stratix® IV FPGAs
    Stratix® V FPGAs

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.