Article ID: 000082227 Content Type: Troubleshooting Last Reviewed: 09/27/2018

Why is the reset controller not behaving correctly when performing a reset via the Avalon®-MM interface in the E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP?

Environment

  • Intel® Stratix® 10 TX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Ethernet
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem with the code generation for the E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP version 18.0 an incorrect connection is made in the file alt_ehipc3_sl_soft.sv for the reset controller. 

    Resolution

    To work around this problem, perform the following changes in the file <IP Folder>/alt_ehipc3_180/synth/alt_ehipc3_sl_soft.sv:

    From:

                .soft_tx_rst_in            (i_sl_soft_csr_rst),

                .soft_rx_rst_in            (i_sl_soft_tx_rst),

                .soft_csr_rst_in           (i_sl_soft_rx_rst),

    To:

                .soft_tx_rst_in            (i_sl_soft_tx_rst),

                .soft_rx_rst_in            (i_sl_soft_rx_rst),

                .soft_csr_rst_in           (i_sl_soft_csr_rst),

     

    This problem has been fixed starting in v18.0.1 of the E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP.

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