Article ID: 000082092 Content Type: Troubleshooting Last Reviewed: 09/03/2018

Why does the TX, RX and CSR reset not work correctly when using the Intel® Stratix® 10 FPAG E-Tile Hard IP for Ethernet Intel® FPGA IP Core?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Ethernet
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    When using the Intel® Stratix® 10 FPGA E-Tile Hard IP for Ethernet Intel® FPGA IP Core, the TX, RX and CSR resets do not work correctly due to an error in the file alt_ehipc3_sl_soft.sv, the following signals are connected as below:

              .soft_tx_rst_in            (i_sl_soft_csr_rst),

              .soft_rx_rst_in            (i_sl_soft_tx_rst),

              .soft_csr_rst_in          (i_sl_soft_rx_rst),

    This has been confirmed as a bug. 

    Resolution

    To work around this problem use the signals in the following manner: 

    1.  To reset the soft_tx-rst_in use i_sl_soft_csr_rst

    2. To reset the soft_rx_rst_in use i_sl_soft_tx_rst 

    3. To reset the soft_csr_rst_in use i_sl_soft_rx_rst

    This problem has been fixed starting in Intel® Quartus® Prime software version 18.0 update 1.

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 TX FPGA

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