Article ID: 000082086 Content Type: Troubleshooting Last Reviewed: 09/11/2012

What is the maximum external clock output frequency for a Stratix enhanced PLL (-5 speed grade) driving a dedicated output clock pin using the LVDS I/O standard?


  • PLL
    Description In the Stratix Handbook version 3.1, Sep 2004, the Stratix Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins in Flip-Chip Packages table lists the maximum output clock rate as 500 MHz, for all Stratix speed grades. The Enhanced PLL Specifications for -5 Speed Grades table shows the fout_ext (maximum output frequency for external clocks) parameter to be 526 MHz.

    The reason for the difference is that the enhanced PLLs have a maximum output clock rate of 526 MHz when driving their dedicated clock output pins. This maximum output clock rate is further constrained depending on the I/O standard used on the PLL_OUT pin and also the device package. For example, in flip-chip packages, the maximum LVDS output clock rate is 500 MHz for a -5 speed grade device. In wire-bond packages, the maximum LVDS output clock rate is 311 MHz for a -5 speed grade device.

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