Description
This problem may occur during a gate-level timing simulation when the clock frequency of an SCFIFO Megafunction is greater than 400MHz. This problem is due to incorrect timing values in the SDO file generated by the netlist writer in the Quartus® II software version 5.1 SP1.
This problem has been fixed beginning with the Quartus II software version 6.0.
Patch 1.14 is also available to fix this problem for version 5.1 SP1. Contact Altera Applications for the patch.
This problem does not occur when you simulate your design in the Quartus II software.