Article ID: 000081961 Content Type: Troubleshooting Last Reviewed: 12/31/2013

Are there any extra requirements when performing dynamic reconfiguration of the CMU PLL to data rates above 4Gbps in Arria V GX ES devices?

Environment

  • Arria® V FPGAs and SoC FPGAs
  • Arria® V GX FPGA
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

Yes, when performing dynamic reconfiguration of the CMU PLL to data rates above 4Gbps in Arria® V GX ES devices you need to execute additional transactions to complete the reconfiguration sequence.

The following pseudo-code provides an example of the additional transaction sequence required on the reconfiguration controller management interface.

  1. write_reg(0x030, 5); // Select the logical address of the CMU PLL ie 5
  2. write_reg(0x033, 0); // Write 0 to address register
  3. write_reg(0x034, 0); // Write 0 to data register
  4. write_reg(0x032, 1); // Trigger write operation

Refer to the Arria V ES Errata for other requirements when operating the CMU PLL above 4Gbps data rates.

This additional sequence is not required for Arria V GX production devices

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