Article ID: 000081955 Content Type: Troubleshooting Last Reviewed: 06/17/2023

Why do the “n” leg of the transceivers within the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel® FPGA IP not appear in the .pin file?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Ethernet
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 18.1 and earlier, the “n” leg of the transceivers within the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel FPGA IP do not appear in the .pin file.

    Resolution

    This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 18.1.1.

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 TX FPGA
    Intel® Stratix® 10 MX FPGA

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