Article ID: 000081955 Content Type: Troubleshooting Last Reviewed: 10/24/2018

Why do the “n” leg of the transceivers within the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel® FPGA IP not appear in the .pin file?

Environment

  • Intel® Stratix® 10 TX FPGA
  • Intel® Stratix® 10 MX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Ethernet
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    Description

    Due to a problem in the Intel® Quartus® Prime software version 18.1 and earlier, the “n” leg of the transceivers within the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel FPGA IP do not appear in the Quartus .pin file.

    Resolution

    This problem is scheduled to be fixed in a future release of the Intel Quartus Prime software.

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