Article ID: 000081919 Content Type: Troubleshooting Last Reviewed: 06/16/2015
Why is my Arria V QDR II and QDRII SRAM controller with UniPHY IP missing a CQn clock signal ?
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Description The Arria® V architecture does not support a complementary CQ clock. Instead, both edges of the CQ clock are used to capture the read data.