Article ID: 000081919 Content Type: Troubleshooting Last Reviewed: 06/16/2015

Why is my Arria V QDR II and QDRII SRAM controller with UniPHY IP missing a CQn clock signal ?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description The Arria® V architecture does not support a complementary CQ clock. Instead, both edges of the CQ clock are used to capture the read data.

Related Products

This article applies to 5 products

Arria® V FPGAs and SoC FPGAs
Arria® V GX FPGA
Arria® V GT FPGA
Arria® V ST SoC FPGA
Arria® V SX SoC FPGA

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