Article ID: 000081776 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Is the DPA lock signal an indication of data pass/fail in Stratix II, Stratix II GX, and Arria GX devices?



No, the DPA lock signal is not an indication of data pass/fail in Stratix® II, Stratix II GX, and Arria® GX devices.

The DPA lock signal indicates 1 or 2 (depending on the altlvds configuration) changes of phase. Once the DPA phase tap selection moves 45 or 90 degrees from its original lock phase, the DPA lock de-asserts. It will not re-assert until the DPA phase tap selection moves within 1 or 2 phase taps of its original lock phase.

Alternatively, you can assert RX_RESET to reset the DPA and allow it to lock to a new phase tap that is optimal for the current conditions of the interface.

Altera® recommends using error detection logic to check for data errors because the phase change may or may not imply a data failure.

Related Products

This article applies to 2 products

Stratix® II GX FPGA
Stratix® II FPGAs