Are single-bit errors corrected when the Enable Error Detection and Correction Logic option is selected, and the Enable Auto Error Correction option is disabled in DDR3 SDRAM Controller with UniPHY Intel® FPGA IP?

When using DDR3 SDRAM Controller with UniPHY Intel® FPGA IP, the Enable Error Detection and Correction Logic option is enabled. Any data coming back from memory via read command with single-bit errors will be corrected automatically regardless of whether the auto-correction feature is enabled or not. This is done by the decoder, which performs single-bit error corrections.

The Enable Auto Error Correction option is an extra feature to enable another read-modify-write process to correct the single-bit error in the memory device.

The Enable Error Detection and Correction Logic option can only correct the read data, not the written data, at the memory device.