Article ID: 000081642 Content Type: Troubleshooting Last Reviewed: 04/28/2015

Why does my Cyclone V PCIe design have intermittent link up issue?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Quartus® II software version 13.0sp1 and earlier have incorrect settings for the Receiver Common Mode Voltage (Vcm) and the Receiver Signal Detection Voltage Threshold (Vth) for the Cyclone® V PCI Express® Hard IP core.  This may cause the PCIe® link to not link train or link up to the maximum lane width.

    Resolution

    1)     Add the following INI variables to a quartus.ini file to enable manual QSF settings for Vcm and Vth.

    ignore_cv_sd_threshold_rule = on

    ignore_cv_sd_vcm_sel_rule = on

    2)     Place this quartus.ini file in the following directory:

    <Working_Directory>/

    3)     Set the Vcm to 0.65V by adding the following QSF assignment:

    set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P65V -to <your_rx_pin_names>

    4)     Set the Vth.

             If VCCR/VCCT_GXB is 1.1V, set the Vth to 35mV by adding the following QSF assignment:

    set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to <your_rx_pin_names>

             If VCCR/VCCT_GXB is 1.2V, set the Vth to 30mV by adding the following QSF assignment:

    set_instance_assignment -name XCVR_RX_SD_THRESHOLD 3 -to <your_rx_pin_names>

     

    Related Products

    This article applies to 3 products

    Cyclone® V GT FPGA
    Cyclone® V FPGAs and SoC FPGAs
    Cyclone® V GX FPGA

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