Article ID: 000081583 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why doesn't the Quartus II software give debugging information when a “Can’t fit design in device” error is reported during I/O Analysis of Stratix III designs containing DDR2 interfaces?



The Quartus® II Software versions 7.2 SP2 and earlier may not generate sub error messages to explain the root causes of a no-fit error, when it is generated during the I/O Analysis phase of the Fitter.

The Fitter should report information such as the following:

Extra Info: Cant globally route 1 more signal(s) into a region 9 global signals have been allocated to the region but the hardware only allows 9 global signals

There can be many causes for no-fits. Altera recommends that you check all design guidelines with regard to I/O assignments and clock / PLL usage. If you encounter problems debugging the cause of a no-fit error, you can contact Altera Technical support by submitting a service request via MySupport on

The problem of debugging messages not being reported is scheduled to be fixed in the next release of the Quartus II software.

Related Products

This article applies to 1 products

Stratix® III FPGAs