Article ID: 000081552 Content Type: Troubleshooting Last Reviewed: 01/30/2015

Errors in ModelSim SE 10.3c and 10.3d when simulating Arria 10 device designs in the Quartus II software version 14.1

Environment

    Quartus® II Subscription Edition
    PLL
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

When simulating the Quartus II software version 14.1 in Mentor Graphics ModelSim SE version 10.3c or 10.3d, designs including cascading phase-locked loops (PLLs) and targeting the Arria 10 device cause simulation errors. Downstream PLLs do not lock and generate incorrect frequencies.

Resolution

You must use the debug version (-novopt) when elaborating in Modelsim.

Related Products

This article applies to 1 products

Intel® Arria® 10 FPGAs and SoC FPGAs

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