Critical Issue
Description
In designs containing multiple PMA Blocks with LVDS I/O, the LVDS channels from different Triple-Speed Ethernet MegaCore functions fail to share a common PLL.
This issue affects designs that contain the Stratix II, Stratix II GX, Stratix III and Stratix IV E/GX device families.
Resolution
No workaround.This issue is fixed in version 11.0 of the Triple-Speed Ethernet MegaCore function.