How do I instantiate a GLOBAL primitive in the LeonardoSpectrum software?

Below are examples of instantiating a GLOBAL primitive in both Verilog HDL and VHDL:

Verilog HDL: Use the ports a_in and a_out when port mapping within the instantiation:

module global_test(test_in, test_out);
input test_in;
output test_out;

GLOBAL test(.a_in(test_in), .a_out(test_out));

endmodule

VHDL: Declare a component with the ports a_in and a_out, and then use these ports in your port mapping:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY global_test IS
PORT ( test_in : in STD_LOGIC ;
test_out : out STD_LOGIC);
END global_test;

ARCHITECTURE a OF global_test IS

COMPONENT global 
PORT ( a_in:  in STD_LOGIC; 
a_out  :  out STD_LOGIC);
END COMPONENT;

BEGIN
u1: global
PORT MAP (test_in, test_out);
END a;