The hardware default setting of Cyclone® IV GX FPGA Development Kit is set to SGMII interface mode. The Marvel 88E1111 Ethernet PHY interfaces the Cyclone IV GX device with RGMII, so you must overwrite the interface settings through the MDIO register of the PHY device. To set it to the RGMII interface mode, follow the procedure below.
Write 0xB to HWCFG_MODE (Register 27, bit[3:0])
Write 0x1 to RGMII Receive Timing Control (Register 20, bit)
Write 0x1 to RGMII Transmit Timing Control (Register 20, bit)
Write 0x1 to Reset (Registe 0, bit , Self-clearing bit)