Article ID: 000081413 Content Type: Troubleshooting Last Reviewed: 06/01/2010

Why do I get a mismatch in Formal Verification when there are flexible LVDS functions in my design?


  • Verification

    When you have flexible LVDS functions in your Cyclone® or Cyclone II design, you may get a mismatch in formal verification with the Cadence Conformal LEC tool. The problem occurs when LVDS receiver instantiated in the design has an odd deserialization factor.

    The Quartus® II software uses an altsyncram megafunction for these LVDS functions. The altsyncram megafunctions that are used during synthesis are not treated as black boxes for formal verification, resulting in many registers in the formal verification netlist file (*.vo) that cause mismatches between the golden and revised netlists in Conformal LEC. 

    To avoid this problem, use the following steps to create a black box for the altsyncram entity that is inferred for the LVDS function.

    1. Find the corresponding altsyncram function in the Quartus II Project Navigator window.<
    2. Add Preserve Hierarchy and black box assignments for each module. For example, these assignments create the following Tcl commands in the Quartus II Settings File (*.qsf) for a design containing an altsyncram function called altsyncram_l7v:
      • set_instance_assignment -name PRESERVE_HIERARCHICAL_BOUNDARY FIRM -to | -entity altsyncram_l7v
      • set_instance_assignment -name EDA_FV_HIERARCHY BLACKBOX -to | -entity altsyncram_l7v
    3. Recompile the design.

    Related Products

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    Cyclone® FPGAs