Article ID: 000081407 Content Type: Troubleshooting Last Reviewed: 08/20/2013

What is the address of the "Write to the 'write' bit of the control and status register" in "Table 8: Using the Register-Based Reconfiguration Method to Reconfigure VOD Settings" of AN676?

Environment

  • Cyclone® V SX SoC FPGA
  • Cyclone® V GT FPGA
  • Stratix® V GX FPGA
  • Stratix® V GT FPGA
  • Cyclone® V GX FPGA
  • Stratix® V GS FPGA
  • Arria® V GZ FPGA
  • Arria® V SX SoC FPGA
  • Cyclone® V ST SoC FPGA
  • Arria® V ST SoC FPGA
  • Arria® V GX FPGA
  • Arria® V GT FPGA
  • Quartus® II Subscription Edition
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    Description

    "Table 8: Using the Register-Based Reconfiguration Method to Reconfigure VOD Settings" of AN676 incorrectly lists the Memory Map Address of the "Write to the 'write' bit of the control and status register" as 0x4A.

    The correct Memory Map Address is 0x0A.

    Resolution

    The incorrect Memory Map Address will be corrected in a future release of AN676.

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