Article ID: 000081366 Content Type: Error Messages Last Reviewed: 12/03/2014

Warning (177007): PLL(s) placed in location &ltPLL location&gt do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks

Environment

  • Quartus® II Subscription Edition
  • PLL
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description You may see the above warning message when you compile the generated example design of the UniPHY-based DDR3 memory controller.
    Resolution

    This warning will show up when user doesn\'t specify whether they are willing to have feedback and output paths differently.  Quartus will try to match both paths with the same compensation path.  This warning can be fixed by setting the following QSF assignment:

    set_instance_assignment -name MATCH_PLL_COMPENSATION_CLOCK OFF -to *

    Related Products

    This article applies to 5 products

    Cyclone® V SX SoC FPGA
    Cyclone® V GT FPGA
    Cyclone® V GX FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SE SoC FPGA

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