Article ID: 000081320 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Are there any issues with respect to HardCopy II devices regarding low M counter PLL settings and the lock detect circuit reporting loss of lock when the Enhanced or Fast PLLs are still frequency locked?

Environment

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Description

Yes, a lock circuit failure may occur in Stratix® II, Stratix® II GX, and HardCopy® II devices for certain M counter and charge pump current (ICP) setting combinations for both Enhanced and Fast PLLs.

Refer to the Stratix II FPGA Family Errata Sheet (PDF) for more information.

Related Products

This article applies to 2 products

HardCopy™ III ASIC Devices
Stratix® II FPGAs

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