Article ID: 000081220 Content Type: Troubleshooting Last Reviewed: 05/13/2016

Driver Margining Not Compatible with Periodic OCT Recalibration in Arria 10 EMIF IP

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    In the Quartus Prime software version 16.0 (Standard and Pro Editions), the Periodic OCT Recalibration feature is enabled automatically for DDR4 designs whenever possible. This feature is not compatible with the Driver Margining feature of the debug toolkit, which measures the timing margin for a memory interface using a traffic pattern generator.

    Resolution

    The workaround for this issue is to disable Periodic OCT Recalibration when generating the EMIF IP if the design is to be used with driver margining.

    This problem will be fixed in a future version.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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