Article ID: 000081211 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Is there any known issue with the DCLK slew rate setting for Cyclone III devices in Quartus II software version 7.1?



Yes, there is a problem with the DCLK slew rate setting for Cyclone® III devices in Quartus® II software version 7.1. The software incorrectly sets a slower DCLK slew rate in user mode for Cyclone III active serial (AS), and active parallel (AP) configuration schemes. The DCLK slew rate is correct during configuration. The DCLK has a slower slew in user mode than during configuration. When operating correctly, the DCLK slew rate should remain unchanged between configuration and user mode.

With version 7.1, the impact on design performance depends on the frequency (Fmax) of the design interfacing with the flash device, and the board design.  The closer the design is to the maximum design specifications, the more likely a performance impact will be observed.

This issue impacts your design only if you use the flash interface during user mode with Cyclone III AS or AP configuration schemes.

This problem is fixed beginning with the Quartus II software version 7.1 SP1.

Related Products

This article applies to 1 products

Cyclone® III FPGAs