Article ID: 000081126 Content Type: Troubleshooting Last Reviewed: 03/28/2023

In the Platform Designer, why are the Triple Speed Ethernet IP core clock names not described in the user guide?

Environment

    Quartus® II Subscription Edition
    Triple-Speed Ethernet Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The Triple Speed Ethernet User Guide describes the clock names used in the parameter editor configuration.

 

The Platform Designer uses the following clock names:

 

  • control_port_clock_connection
  • pcs_mac_tx_clock_connection
  • pcs_mac_rx_clock_connection
  • receive_clock_connection
  • transmit_clock_connection
Resolution

The following Platform Designer clock names are equivalent to the clock names in the parameter editor:

  • control_port_clock_connection -> clk
  • pcs_mac_tx_clock_connection -> tx_clk
  • pcs_mac_rx_clock_connection -> rx_clk
  • receive_clock_connection -> ff_rx_clk
  • transmit_clock_connection -> ff_tx_clk

Related articles

Related Products

This article applies to 37 products

Intel® Stratix® 10 SX SoC FPGA
Cyclone® IV E FPGA
Arria® V SX SoC FPGA
Arria® V ST SoC FPGA
HardCopy™ IV E ASIC Devices
Cyclone® III LS FPGA
Stratix® IV E FPGA
Cyclone® V GT FPGA
Cyclone® III FPGAs
Stratix® V GX FPGA
Cyclone® IV GX FPGA
Cyclone® II FPGA
Cyclone® V GX FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Stratix® II GX FPGA
Stratix® II FPGAs
Arria® V GX FPGA
Stratix® V GT FPGA
Intel® Arria® 10 GT FPGA
Arria® V GT FPGA
Stratix® IV GX FPGA
Stratix® III FPGAs
Arria® II GX FPGA
Intel® Arria® 10 GX FPGA
Arria® II GZ FPGA
Stratix® IV GT FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
Intel® Arria® 10 SX SoC FPGA
Arria® GX FPGA
HardCopy™ III ASIC Devices
Cyclone® V SX SoC FPGA
Cyclone® V ST SoC FPGA
HardCopy™ IV GX ASIC Devices
Cyclone® V SE SoC FPGA
Intel® Stratix® 10 GX FPGA

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.