Description
The TSE User Guide describes the clock names used in the IP Catalog flow for devices released prior to Arria® 10.
Resolution
The following Qsys clock names are equivalent to the documented clock names:
control_port_clock_connection = clk
receive_clock_connection = ff_rx_clk
transmit_clock_connection = ff_tx_clk
pcs_ref_clk_clock_connection = ref_clk
tx_serial_clk = comes for the external TXPLL
rx_cdr_refclk = ref_clk
In Arria 10 the TX PLL is external to the TSE IP and must be manually generated and connected by user RTL. You must configure the Arria 10 Transceiver ATX PLL with an output clock frequency of 1250.0 MHz.
