Article ID: 000081035 Content Type: Troubleshooting Last Reviewed: 01/02/2014

Can I simulate the hard ECC functionality in Altera RAM blocks?

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Description

No, the simulation models for Altera RAM blocks do not support simulation of the hard Error-Correction Code (ECC) functionality.  In simulation, the eccstatus outputs for these RAM blocks are always low.

This applies to all Altera devices with RAM blocks that contain hard ECC functionality including Stratix® series devices beginning with Stratix III, Arria® series devices beginning with Arria II, Cyclone® series devices beginning with Cyclone V, and HardCopy® series devices beginning with HardCopy III.

Related Products

This article applies to 23 products

Stratix® III FPGAs
Stratix® IV E FPGA
Stratix® IV GT FPGA
Stratix® V E FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA
Arria® II GZ FPGA
Stratix® IV GX FPGA
Arria® II GX FPGA
Arria® V GX FPGA
Cyclone® V GT FPGA
Arria® V GT FPGA
Cyclone® V E FPGA
Cyclone® V GX FPGA
Arria® V SX SoC FPGA
Arria® V ST SoC FPGA
Cyclone® V SE SoC FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SX SoC FPGA
HardCopy™ III ASIC Devices
HardCopy™ IV E ASIC Devices
HardCopy™ IV GX ASIC Devices

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