Article ID: 000080977 Content Type: Error Messages Last Reviewed: 04/11/2023

Error: Channel PLL Parameter 'output_clock_frequency' is set to an illegal value of '<Channel PLL output frequency> MHz' and PMA Direct parameter is set to 'false'.

Environment

    Quartus® II Subscription Edition
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Description

You may encounter the above Quartus® II fitter error if you use the Cyclone® V Custom PHY with a transceiver speed grade of -6 and a core speed grade of -7 in Quartus® II software version 13.0. This is due to an incorrectly mapped transceiver speed grade.

Resolution

To work around this problem, you should upgrade to Quartus® II software version 13.0sp1.

Related Products

This article applies to 4 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Cyclone® V GX FPGA
Cyclone® V ST SoC FPGA

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