Rule Violation Warnings During Compilation

If you compile your designs using DDR or DDR2 SDRAM Controller version 9.1 and later, you get the following rule violation warnings:

Rule A103: Design should not contain delay chains.

Rule C104: Clock signal source should drive only clock input ports.

Rule R105: The reset signal that is generated in one clock domain and used in another clock domain should be synchronized.

Rule C106: Clock signal source should not drive registers triggered by different clock edges.

This issue affects all designs that use the DDR or DDR2 SDRAM Controller version 9.1 and later.

Use the high-performance controllers with ALTMEMPHY or UniPHY instead.

This issue will not be fixed.