Article ID: 000080958 Content Type: Troubleshooting Last Reviewed: 08/15/2023

Why are the Intel® Arria® 10 IOPLL output clocks aligned with the falling edge not the rising edge of the reference clock?

Environment

  • Intel® Quartus® Prime Pro Edition
  • IOPLL Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to the problem in Quartus® Prime Software, the IOPLL simulation model will show the output clock's edge aligned to the falling edge of the reference clock, not the rising edge of the reference clock.

     

     

    Resolution

    This is not the behavior that you would see in silicon. It is a bug in the simulation model and does not affect hardware. The TimeQuest will analyze the timing with respect to the rising edge of the reference clock.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs