Due to the problem in Quartus® Prime software, IOPLL simulation model will show the output clocks edge alligned to the falling edge of the reference clock, not the rising edge of the reference clock.
This is not the behavior that you would see in silicon. It is a bug in the simulation model, and does not affect hardware. The TimeQuest will analyse the timing with respect to rising edge of the reference clock. This will be fixed in later Quartus® version.