Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.1, you may see this error message when your design has the next three conditions:
- The design has an instance of the Signal Tap logic analyzer or the In-System Sources and Probes with synchronous transfers.
- A clock port in the design is named using the following naming convention clk_<digits>. For example: clk_100.
- The number of clocks in the design is greater than the value represented by <digits>.
To avoid this problem, verify the names used in the design for the clock ports and avoid a naming convention as clk_<digits>.
This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.2.