Article ID: 000080892 Content Type: Troubleshooting Last Reviewed: 06/30/2014

Why does the XCVR_REFCLK_PIN_TERMINATION, DC_COUPLING_INTERNAL_100_OHM assignment fail in Quartus® software version 12.0?

Environment

  • Stratix® V GX FPGA
  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The XCVR_REFCLK_PIN_TERMINATION, DC_COUPLING_INTERNAL_100_OHM assignment fails in Quartus® software version 12.0 due to a typing error in the transceiver PHY IP userguide.

    "Table 6-4. Transceiver and PLL Assignments for Stratix® V Devices" of the transceiver PHY IP userguide details the constraint as"DC_COUPLING_INTERNAL_100_OHM". The correct constraint is "DC_COUPLING_INTERNAL_100_OHMS"

    This documentation error will be fixed in a future release of the user guide.

    Resolution

     

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