Article ID: 000080870 Content Type: Troubleshooting Last Reviewed: 04/29/2019

Why does the design example simulation not complete for E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP variant when selecting “AN/LT” and “PCS_only” options?

Environment

  • Intel® Quartus® Prime Pro Edition
  • E-tile Hard IP for Ethernet Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime software version 19.1 and earlier, the design example testbench for E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP variant  with “AN/LT” and “PCS_only” options selected will not complete. 

    Resolution

    To work around this problem, perform the following steps:

            1.)   Navigate to the alt_ehip3_0_example_design/example_testbench directory

            2.)   Open the “basic_avl_tb_top.sv” file

            3.)   Change line 461 FROM:

                            #5000 i_reconfig_clk = ~i_reconfig_clk;

                    TO:

                            #500 i_reconfig_clk = ~i_reconfig_clk;

            4.)   Rerun simulation

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 TX FPGA

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