Critical Issue
Due to a problem with the Intel® Quartus® Prime Standard software version 18.0 and onwards, when enabling burst capability for RXM BAR2 port of the Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon®-MM DMA interface for PCI Express* IP, the following Analysis & Synthesis error will occur.
Error (10166): SystemVerilog RTL Coding error at altpcieav_dma_hprxm_rdwr.sv(562): always_comb construct does not infer purely combinational logic.
Error (12152): Can't elaborate user hierarchy "*|altpcieav_256_app:g_avmm_256_dma.avmm_256_dma.altpcieav_256_app|altpcieav_dma_hprxm:hprxm_master|altpcieav_dma_hprxm_rdwr:hprxm_pcie_rdwr"
Modify the verilog file below at the line_602 to fix the problem as follows.
File Path :\ip\altera\altera_pcie\altera_pcie_hip_256_avmm\rtl\altpcieav_dma_hprxm_rdwr.sv
From :
default: avmm_fbe[15:0] = 16'hFFFF;
To :
default : begin
avmm_fbe[15:0] = 16'hFFFF;
first_dw_holes = 10'h0;
end
This problem is scheduled to be fixed in the Intel® Quartus® Prime Standard software version 18.1 update1 or later.