Article ID: 000080851 Content Type: Troubleshooting Last Reviewed: 03/06/2019

Why does the Intel® Arria® 10 DisplayPort IP with Bitec* daughter card have no video output for both 1 lane or 2 lanes configurations?

Environment

  • Intel® Quartus® Prime Pro Edition
  • DisplayPort Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with the Intel® Arria® 10 DisplayPort IP in the Intel® Quartus® Prime Pro edition version 17.1, DisplayPort IP configured for 1 lane or 2 lanes will not have a video output  when paired with Bitec* daughter card rev8 and below.

    This is due to DisplayPort IP core transmitting the video through lanes fmca_dp_c2m_n[0] & fmca_dp_c2m_n[1] when it is set to 2 lanes. The signals are mapped to lane 2 & 3 of the Bitec daughter card's DisplayPort Transmitter connector for  lane reversal and polarity inversion support. The DisplayPort sink (monitor) is expecting display port training patterns at lane 0 and 1 of the DisplayPort connector only. Hence, this results the link training between DisplayPort source-sink will fail and end up with no video output failure. 

     

     

     

    Resolution

    To work around tis problem, manually remap DisplayPort IP lane[0] and lane[1] pin location assignment with reference to the table guideline.

     

    Step 1 : Disable all of the XCVR_RECONFIG_GROUP on channel 0 to 3 in the QSF. 

    For instance :

    set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to fmca_dp_c2m_p[0] -entity a10_dp_demo

    set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to fmca_dp_m2c_p[0] -entity a10_dp_demo

     

    Step 2 : Modify DisplayPort IP lane pin assignment in the QSF as per the table guideline

     

    This problem will be fixed in a future version of the Intel® Quartus® Prime Pro software.

     

     

        

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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