Why does ModelSim* simulator stop unexpectedly when simulating the 25G Ethernet Intel® FPGA IP Design Example with "enable 10G/25G dynamic rate switching"?

Due to a problem with the 25G Ethernet Intel® FPGA IP in Intel Quartus® Prime Pro edition version 18.1, the design example with "enable 10G/25G dynamic rate switching"  selected may stop unexpectedly in the ModelSim* simulator.  

The ModelSim transcript stops at the simulation stages below:

• # Switching to 25G mode : 25G Reconfig start
• # Switching to 25G mode : 25G Reconfig End
  
• #Waiting for RX alignment  

To work around this problem, modify run_vsim.do of the example design in the following directory

• alt_e25s10_0_example_design\example_testbench\run_vsim.do

In run_vsim.do, find "elab" and replace with "elab_debug"

• elab to elab_debug

This problem is scheduled to be fixed in a future version of the Intel® Quartus® Prime Pro software.