Article ID: 000080844 Content Type: Troubleshooting Last Reviewed: 06/10/2019

Why does ModelSim* simulator stop unexpectedly when simulating the 25G Ethernet Intel® FPGA IP Design Example with "enable 10G/25G dynamic rate switching"?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • 25G Ethernet Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem with the 25G Ethernet Intel® FPGA IP in Intel Quartus® Prime Pro edition version 18.1, the design example with "enable 10G/25G dynamic rate switching"  selected may stop unexpectedly in the ModelSim* simulator.  

    The ModelSim transcript stops at the simulation stages below:

    • # Switching to 25G mode : 25G Reconfig start
    • # Switching to 25G mode : 25G Reconfig End
    • #Waiting for RX alignment  

     

    Resolution

    To work around this problem, modify run_vsim.do of the example design in the following directory

    • alt_e25s10_0_example_design\example_testbench\run_vsim.do

    In run_vsim.do, find "elab" and replace with "elab_debug"

    • elab to elab_debug

    This problem is scheduled to be fixed in a future version of the Intel® Quartus® Prime Pro software.

     

     

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