Article ID: 000080844 Content Type: Troubleshooting Last Reviewed: 02/20/2023

Why does ModelSim* simulator stop unexpectedly when simulating the 25G Ethernet Intel® FPGA IP design example with "enable 10G/25G dynamic rate switching"?

Environment

  • Intel® Quartus® Prime Pro Edition
  • 25G Ethernet Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem with the 25G Ethernet Intel® FPGA IP in the Intel® Quartus® Prime Pro Edition Software version 18.1, the design example with "enable 10G/25G dynamic rate switching"  selected might stop unexpectedly in the ModelSim* simulator.  

    The ModelSim transcript stops at the following simulation stages:

    • # Switching to 25G mode : 25G Reconfig start
    • # Switching to 25G mode : 25G Reconfig End
    • #Waiting for RX alignment  

     

    Resolution

    To work around this problem, modify run_vsim.do of the design example in the following directory:

    • alt_e25s10_0_example_design\example_testbench\run_vsim.do

    In run_vsim.do, find "elab" and replace with "elab_debug"

    • elab to elab_debug

    This problem is scheduled to be fixed in a future version of the Intel® Quartus® Prime Pro Edition Software.

     

     

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs