Why does the Low Latency 100G Ethernet Intel® FPGA IP fail timing on Intel® Stratix® 10 FPGA?

When using the Low Latency 100G Ethernet Intel® FPGA IP with RSFEC and/or KR mode enabled on Intel® Stratix® 10 FPGA, timing violations can be observed.

To work around these timing violations when using Intel® Quartus® Prime version 18.0 or 18.1:

• a. Check the Low Latency 100G Ethernet Intel® FPGA IP placement using the Quartus Prime Chip Planner.
  • If any hard block in the core is in the way of the placement of the Intel® Stratix® 10 100G IP placement, it may create long routing and result in bad timing.
  • If this is the case, please choose a different set of transceiver locations when possible.
• b. Try seed sweeping to get a better timing result.

This problem has been improved but not fixed in version 19.1 of the Intel® Quartus® Prime Edition Software.