Article ID: 000080842 Content Type: Troubleshooting Last Reviewed: 01/11/2023

Why does the Low Latency 100G Ethernet Intel® FPGA IP fail timing on Intel® Stratix® 10 FPGA?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Low Latency 100G Ethernet Intel® FPGA IP for Arria® 10 and Stratix® V
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    Critical Issue

    Description

    When using the Low Latency 100G Ethernet Intel® FPGA IP with RSFEC and/or KR mode enabled on Intel® Stratix® 10 FPGA, timing violations can be observed.

    Resolution

    To work around these timing violations when using Intel® Quartus® Prime version 18.0 or 18.1:

    • a. Check the Low Latency 100G Ethernet Intel® FPGA IP placement using the Quartus Prime Chip Planner.
      • If any hard block in the core is in the way of the placement of the Intel® Stratix® 10 100G IP placement, it may create long routing and result in bad timing.
      • If this is the case, please choose a different set of transceiver locations when possible.
    • b. Try seed sweeping to get a better timing result.

    This problem has been improved but not fixed in version 19.1 of the Intel® Quartus® Prime Edition Software.

    Related Products

    This article applies to 4 products

    Intel® Stratix® 10 GX FPGA
    Intel® Stratix® 10 SX SoC FPGA
    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 TX FPGA

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