Article ID: 000080840 Content Type: Troubleshooting Last Reviewed: 05/23/2019

Why can’t I generate 2 or 3 channel E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP when "1 to 4 10GE/25GE with optional RSFEC" or "100GE or 1 to 4 10GE/25GE with optional RSFEC and 1588 PTP" core variant are selected and "Enable AN/LT" is enabled?

Environment

  • Intel® Agilex™ F-Series FPGAs and SoC FPGAs
  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Quartus® Prime Pro Edition
  • E-tile Hard IP for Ethernet Intel® FPGA IP
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    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime software version 19.1, the number of channels that are allowed to be created when using the E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP when "1 to 4 10GE/25GE with optional RSFEC" or "100GE or 1 to 4 10GE/25GE with optional RSFEC and 1588 PTP" core variant are selected and "Enable AN/LT" is enabled, is incorrectly limited to just 1 or 4 channel configurations.

    Resolution

    This problem has been fixed starting in the 19.2 release of the Intel® Quartus® Prime software.

    Up to (4) channels will then be allowed for these configurations of the IP when "Enable AN/LT" has been selected.

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