Due to a problem in the Intel® Quartus® Prime Pro Edition Software, if you generate an IP megacore with VHDL selected, you may encounter these errors when compiling for simulation:
# ** Error: .<your module>.vhd<your line number>: (vcom-1133) Type mismatch found on port <your port>".
# In the component "<your component>", the port type is "ieee.std_logic_1164.STD_LOGIC".
# In the entity "<your lower level entity>", the port type is "ieee.std_logic_1164.STD_LOGIC_VECTOR"
To work around this issue you must edit the generated RTL and match the data types in both the top instance and the testbench.
For example, for a module called "FP_TEST", you would do the following:
Make the following changes in <your tb>_tb.vhd
From:
architecture rtl of FP_TEST_tb is
component FP_TEST is
port (
a : in std_logic_vector(63 downto 0) := (others => 'X'); -- a
areset : in std_logic := 'X'; -- reset
b : in std_logic_vector(63 downto 0) := (others => 'X'); -- b
clk : in std_logic := 'X'; -- clk
opSel : in std_logic := 'X'; -- opSel
q : out std_logic_vector(63 downto 0) -- q
);
end component FP_TEST;
...
fp_test_inst : component FP_TEST
port map (
a => fp_test_inst_a_bfm_conduit_a, -- a.a
areset => fp_test_inst_areset_bfm_reset_reset, -- areset.reset
b => fp_test_inst_b_bfm_conduit_b, -- b.b
clk => fp_test_inst_clk_bfm_clk_clk, -- clk.clk
opSel => fp_test_inst_opsel_bfm_conduit_opsel(0), -- opSel.opSel
q => fp_test_inst_q_q -- q.q
);
To:
architecture rtl of FP_TEST_tb is
component FP_TEST is
port (
a : in std_logic_vector(63 downto 0) := (others => 'X'); -- a
areset : in std_logic := 'X'; -- reset
b : in std_logic_vector(63 downto 0) := (others => 'X'); -- b
clk : in std_logic := 'X'; -- clk
opSel : in std_logic_vector(0 downto 0) := (others => 'X'); -- opSel
q : out std_logic_vector(63 downto 0) -- q
);
end component FP_TEST;
fp_test_inst : component FP_TEST
port map (
a => fp_test_inst_a_bfm_conduit_a, -- a.a
areset => fp_test_inst_areset_bfm_reset_reset, -- areset.reset
b => fp_test_inst_b_bfm_conduit_b, -- b.b
clk => fp_test_inst_clk_bfm_clk_clk, -- clk.clk
opSel => fp_test_inst_opsel_bfm_conduit_opsel, -- opSel.opSel
q => fp_test_inst_q_q -- q.q
);
And make the following changes in <your module>.vhd
From:
entity FP_TEST is
port (
a : in std_logic_vector(63 downto 0) := (others => '0'); -- a.a
areset : in std_logic := '0'; -- areset.reset
b : in std_logic_vector(63 downto 0) := (others => '0'); -- b.b
clk : in std_logic := '0'; -- clk.clk
opSel : in std_logic := '0'; -- opSel.opSel
q : out std_logic_vector(63 downto 0) -- q.q
);
end entity FP_TEST;
architecture rtl of FP_TEST is
component FP_TEST_altera_fp_functions_160_xhvb5va is
port (
clk : in std_logic := 'X'; -- clk
areset : in std_logic := 'X'; -- reset
a : in std_logic_vector(63 downto 0) := (others => 'X'); -- a
b : in std_logic_vector(63 downto 0) := (others => 'X'); -- b
q : out std_logic_vector(63 downto 0); -- q
opSel : in std_logic := 'X' -- opSel
);
end component FP_TEST_altera_fp_functions_160_xhvb5va;
To:
entity FP_TEST is
port (
a : in std_logic_vector(63 downto 0) := (others => '0'); -- a.a
areset : in std_logic := '0'; -- areset.reset
b : in std_logic_vector(63 downto 0) := (others => '0'); -- b.b
clk : in std_logic := '0'; -- clk.clk
opSel : in std_logic_vector(0 downto 0) := (others => '0'); -- opSel.opSel
q : out std_logic_vector(63 downto 0) -- q.q
);
end entity FP_TEST;
architecture rtl of FP_TEST is
component FP_TEST_altera_fp_functions_160_xhvb5va is
port (
clk : in std_logic := 'X'; -- clk
areset : in std_logic := 'X'; -- reset
a : in std_logic_vector(63 downto 0) := (others => 'X'); -- a
b : in std_logic_vector(63 downto 0) := (others => 'X'); -- b
q : out std_logic_vector(63 downto 0); -- q
opSel : in std_logic_vector(0 downto 0) := (others => 'X') -- opSel
);
end component FP_TEST_altera_fp_functions_160_xhvb5va;
This is scheduled to be fixed in a future release of the Intel® Quartus® Prime Software.