Can the 128-bit Avalon-MM Txs slave interface of the Altera Hard IP for PCI Express handle read/write request with ByteEnable=0x01 ?

Due to a problem in the Quartus® II software version 13.1 and earlier, the 128-bit Avalon-MM® Txs slave interface of the Hard IP for PCI Express* cannot generate a correct PCI Express TLP packet when the ByteEnable = 0x01, 0x03, or 0x7 at Avalon-MM interface.

Avalon-MM bridges operate correctly with a burst count = 1 and the following byte enables (DW Byte Enable)

16'hF000
16'h0F00
16'h00F0
16'h000F
16'hFF00
16'h0FF0
16'h00FF
16'hFFF0
16'h0FFF
16'hFFFF

To work around this problem, use a 64bit Avalon-MM Txs slave interface, or set ByteEnable to more than 0x07 (set 4 byte enable or more) with a 128-bit Avalon-MM Txs slave interface.

There is currently no plan to fix this problem.