Article ID: 000080736 Content Type: Error Messages Last Reviewed: 09/11/2012

Error: Cruclk [0] input frequency 0.0 MHz of GXB receiver PLL of GXB receiver channel atom "rio_rio:rio_rio_inst|rio_riophy_xcvr:riophy_xcvr|rio_riophy_gxb:riophy_gxb|alt2gxb:alt2gxb_component|channel_rec[0].receive" must be in the frequency range of 50.0

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

During the full compilation, the below error message may be displayed. This is due to incorrect CMU PLL inclock period. You may encounter some simulation problems due to the same issue.

 

To solve this error, open the <project_name>_riophy_gxb.v, change the

alt2gxb_component.cmu_pll_inclock_period = 1000000/input clock frequency from the incorrect value. Then regenerate the IP Functional Simulation model of the RapidIO® MegaCore®.

 

To regenerate an IP Functional Simulation model:

1.      Open a command prompt and direct the path to your project directory.

2.      Type the following command line to regenerate the IP Functional Simulation Model for the IP MegaCore with the quartus_map command line option SIMGEN_RAND_POWERUP_FFS=OFF:

 

quartus_map --simgen --simgen_parameter="CBX_HDL_LANGUAGE=Verilog,SIMGEN_RAND_POWERUP_FFS=OFF" --family=stratixiv \

--source="./rio_rio.v" \

--source="./rio_riophy_gxb.v" \

--source="./rio_phy_mnt.v" \

--source="./rio_riophy_xcvr.v" \

--source="./rio_riophy_dcore.v" \

--source="./rio_riophy_reset.v" \

--source="./rio_concentrator.v" \

--source="./rio_drbell.v" \

--source="./rio_io_master.v" \

--source="./rio_io_slave.v" \

--source="./rio_maintenance.v" \

--source="./rio_reg_mnt.v" \

--source="./rio_transport.v" \

rio.v

 

 

3.      You need to modify the command line based on the correct device and HDL information.

       Example: "CBX_HDL_LANGUAGE=Verilog" or "CBX_HDL_LANGUAGE=HDL"

                      "--family=Stratix® IV" or = one of "Arria® II GX, Cyclone® IV, Arria GX, Stratix II GX"

 

4.  After the command, Quartus® II software will regenerate a new IP Functional Simulation Model file with the changed CMU PLL inclock settings.

 

Error: Cruclk [0] input frequency 0.0 MHz of GXB receiver PLL of GXB receiver channel atom "rio_rio:rio_rio_inst|rio_riophy_xcvr:riophy_xcvr|rio_riophy_gxb:riophy_gxb|alt2gxb:alt2gxb_component|channel_rec[0].receive" must be in the frequency range of 50.0 MHz to 623.1 MHz

Related Products

This article applies to 2 products

Stratix® II GX FPGA
Arria® GX FPGA

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